MC06XSD200FK データシートの表示（PDF） - Freescale Semiconductor
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MC06XSD200FK Datasheet PDF : 60 Pages
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
before the SO registers can be read. The SO register
assignment is described in Table 12.
- 20%) is recommended between these pins and GND for
optimal EMC performances.
POWER SWITCH OUTPUT PINS (HS0 AND HS1)
HS0 and HS1 are the output pins of the power switches, to
be connected to the loads. A ceramic capacitor (<= 22 nF (+/
FAIL-SAFE OUTPUT (FSOB)
This pin (active low) is used to indicate loss of SPI
communication or loss of SPI supply voltage, VDD. This open-
drain output requires an external pull-up resistor to VPWR.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER SUPPLY
internal regulator
MCU
MCU INTERFACE and
INTERFACE OUTPUT CONTROL
SPI INTERFACE
PARALLEL CONTROL
INPUTS
PWM CONTROLLER
SELF-
PROTECTED
HIGH SIDE
SWITCHES
HS0-HS1
POWER SUPPLY
The device operates with supply voltages from 6.0 to 58 V
(VPWR), but is full spec. compliant between 8.0 and 36 V. The
VPWR pin supplies power to the internal regulator, analog,
and logic circuit blocks. The VDD pin (5.0 V typ.) supplies the
output register of the Serial Peripheral Interface (SPI).
Consequently, the SPI registers cannot be read without
presence of VDD. The employed IC architecture guarantees
a low quiescent current in Sleep mode.
SWITCH OUTPUT PINS HS0 & HS1
HS0 and HS1 are the output pins of the power switches.
Both channels are protected against various kinds of short-
circuits and have active clamp circuitry that may be activated
when switching off inductive loads. Many protective and
diagnostic functions are available. For large inductive loads,
it is recommended to use a freewheeling diode. The device
can be configured to control the output switches in parallel,
which guarantees good switching synchronization.
COMMUNICATION INTERFACE AND DEVICE
CONTROL
In Normal mode the output channels can either be
controlled by the direct inputs or by the internal PWM module,
which is configured by the SPI register settings. For
bidirectional SPI communication, VDD has to be in the
authorized range. Failure diagnostics and configuration are
also performed through the SPI port. The reported failure
types are: OpenLoad, short-circuit to supply, severe short-
circuit to ground, overcurrent, overtemperature, clock-fail,
undervoltage, and overvoltage. The SPI port can be supplied
either by a 5.0 V or by a 3.3 V voltage supply. For direct input
control, VDD is not required.
A Pulse Width Modulation (PWM) circuit allows driving
loads at frequencies up to 1.0 kHz from an external or an
internal clock. SPI communication is required to set these
options.
Analog Integrated Circuit Device Data
Freescale Semiconductor
06XSD200
25
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