MC06XSD200FK データシートの表示（PDF） - Freescale Semiconductor
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MC06XSD200FK Datasheet PDF : 60 Pages
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FUNCTIONAL DESCRIPTION
PIN ASSIGNMENT AND FUNCTIONS
mode. Both IN pins are internally connected to a pull-down
resistor.
CONFIGURATION INPUTS (CONF0 AND CONF1)
The CONF[0 :1] input pins allow configuring both channels
for the appropriate load type. CONF = 0 activates the bulb
overcurrent protection profile, and CONF = 1 the DC motor
profile. These inputs are connected to an internal voltage
regulator of 3.3 V by an internal pull-up current source IUP.
Therefore, CONF = 1 is the default value when these pins are
disconnected. Details on how to configure the channels are
given in the table Overcurrent Profile Selection.
FAULT STATUS (FSB)
This open-drain output is asserted low when any of the
following faults occurs (see Fault Mode): overcurrent (OC),
overtemperature (OT), Output connected to VPWR, Severe
short-circuit (SC), OpenLoad in ON state (OL_ON),
OpenLoad in OFF state (OL_OFF), External Clock-fail
(CLOCK_fail), overvoltage (OV), and undervoltage (UV).
Each fault type has its own assigned bit inside the STATR,
FAULTR_s, or DIAGR_s register. Fault type identification
and fault bit reset are accomplished by reading out these
registers. They are part of the SO register (Table 12) and are
accessed through the SPI port.
PWM CLOCK (CLOCK)
This pin is the input for an external clock signal that
controls the internal PWM module.The clock signal is
monitored by the device. The PWM module controls ON-time
and turn-ON delay of the selected channels. The CLOCK pin
should not be confused with the SCLK pin, which is the clock
pin of the SPI interface. CLOCK has an internal pull-down
current source (IDWN) to GND.
RESET (RSTB)
All SPI register contents are reset when RSTB = 0. When
RSTB = 0, the device returns to Sleep mode tIN sec. after the
last falling edge of the last active IN[0:1] signal. As long as the
Reset input (RSTB pin) is at logic 0 and both direct input
states are low, the device remains in Sleep mode (Channel
configuration through the SPI). A 0-to-1 transition on RSTB
wakes up the device and starts a watchdog timer to check the
continuous presence of the SPI signals. To do this, the device
monitors the contents of the first bit (WDIN bit) of all SPI
words following that transition (regardless the register it is
contained in). When this contents is not alternated within a
duration tWDTO, SPI communication is considered lost, and
Fail-safe mode is entered (Entering Fail-safe Mode). RSTB is
internally pulled-down to GND by resistor RDWN.
CHIP SELECT (CSB)
Data communication over the SPI port is enabled when the
CSB pin is in the logic [0] state. Data from the Input Shift
registers are locked in the addressed SI registers on the
rising edge of CSB. The device transfers the contents of one
of the 8 internal registers to the SO register on the falling
06XSD200
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edge of CSB. The SO output driver is enabled when CSB is
logic [0]. CSB should transition from a logic [1] to a logic [0]
state only when SCLK is at logic [0] (Figure 7 and Figure 8).
CSB is internally pulled up to VDD through IUP.
SPI SERIAL CLOCK (SCLK)
The SCLK pin clocks the SPI data communication of the
device. The serial input pin (SI) transfers data to the SI shift
registers on the falling edge of the SCLK signal while data in
the SO registers are transferred to the SO pin on the rising
edge of the SCLK signal. The SCLK pin must be in the low
state when CSB makes any transition. For this reason, it is
recommended to have the SCLK pin in the logic [0] state
when the device is not accessed (CSB is at logic [1]). When
CSB is set to logic [1], signals at the SCLK and SI pins are
ignored and the SO output is tri-stated (high-impedance).
The SCLK pin is connected to an internal pull-down current
source IDWN.
SERIAL INPUT (SI)
Serial input (SI) data bits are shifted in at this pin. SI data
is read on the falling edge of SCLK. 16-bit data packages are
required on the SI pin (see Figure 7), starting with bit D15
(MSB) and ending with D0 (LSB). All the internal device
registers are addressed and controlled by a 4-bit address
(D9-D12) described in Table 10. Register addresses and
function attribution are described in Table 11. The SI pin is
internally connected to a pull-down current source, IDWN.
SUPPLY OF THE DIGITAL CIRCUITRY (VDD)
This pin supplies the SPI circuit (3.3 V or 5.0 V). When
lost, all circuitry becomes supplied by a VPWR derived
voltage, except the SPI’s SO shift-register that can no longer
be read.
GROUND (GND)
This is the GND pin common for both the SPI and the other
circuitry.
POSITIVE SUPPLY PIN (VPWR)
This pin is the positive supply and the common input pin of
both switches. A 100 nF ceramic capacitor must be
connected between VPWR and GND, close to the device. In
addition, it is recommended to put a ceramic capacitor of at
least 1.0 µF in parallel with this 100 nF capacitor.
SERIAL OUTPUT (SO)
The SO pin is a tri-stateable output pin that conveys data
from one of the 13 internal SO registers or from the previous
SI register to the outside world. The SO pin remains in a high-
impedance state (tri-state) until the CSB pin becomes
logic [0]. It then transfers the SPI data (device state,
configuration, fault information). The SO pin changes state at
the rising edge of the SCLK signal. For daisy-chaining, it can
be read out on the falling edge of SCLK. VDD must be present
Analog Integrated Circuit Device Data
Freescale Semiconductor
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