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M312L2828ET0 データシートの表示(PDF) - Samsung

部品番号
コンポーネント説明
一致するリスト
M312L2828ET0
Samsung
Samsung Samsung
M312L2828ET0 Datasheet PDF : 23 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
AC Timming Parameters & Specifications
Parameter
Symbol
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCCD
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup
tDQSH
tDQSL
tDSC
tIS
Address and Control Input hold
tIH
Address and Control Input setup
tIS
Address and Control Input hold
tIH
Data-out high impedence time from CK/
CK
Data-out low impedence time from CK/
CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to
tHZ
tLZ
tSL(I)
tSL(IO)
tSL(O)
tSLMR
AA
(DDR266@CL=2)
Min
Max
60
75
45
120K
15
15
15
15
1
1
7.5
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
-0.75
+0.75
-0.75
+0.75
0.5
0.5
1.0
4.5
0.67
1.5
A2
(DDR266@CL=2)
Min
Max
65
75
45
120K
20
20
15
15
1
1
7.5
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
-0.75
+0.75
B0
(DDR266@CL=2.5)
Min
Max
65
75
45
120K
20
20
15
15
1
1
10
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
-0.75
+0.75
A0
(DDR200@CL=2)
Min
Max
70
80
48
120K
20
20
15
15
1
1
10
12
0.45
0.55
0.45
0.55
-0.8
+0.8
-0.8
+0.8
-
0.6
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
1.1
1.1
1.1
1.1
Unit Note
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
tCK
tCK
ns
ns
ns 12
tCK
tCK
tCK
ns
3
tCK
tCK
tCK
tCK
tCK
tCK
ns i,5.7~9
ns i,5.7~9
ns i, 6~9
ns i, 6~9
-0.8
+0.8 ns
1
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1
0.5
0.5
0.5
V/ns
0.5
0.5
0.5
V/ns
1.0
4.5
1.0
4.5
1.0
4.5 V/ns
0.67
1.5
0.67
1.5
0.67
1.5
Revision 1.4 February, 2004

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