P4C1024L データシートの表示（PDF） - Performance Semiconductor

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P4C1024L

LOW POWER 128K x 8 CMOS STATIC RAM

Performance Semiconductor 

P4C1024L

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)

ADDRESS

CE1

CE2

WE

DATA IN

(12)

DATA OUT

tWC (9)

tAS

tCW

tAW

tAH

tWP

tDW

tDH

DATA VALID

HIGH IMPEDANCE

AC TEST CONDITIONS

TRUTH TABLE

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

Output Timing Reference Level

1.5V

1.5V

Output Load

See Figures 1 and 2

Mode

Standby

Standby

CE

1

CE2

OE

WE

I/O

Power

H X X X High Z Standby

X L X X High Z Standby

D Disabled L H H H High Z Active

OUT

Read

Write

L H L H DOUT Active

L H X L High Z Active

DOUT

990 Ω

+5V

1800 Ω

30pF* (5pF* for t HZ , t LZ , t OHZ,

t OLZ t,WZ and t OW )

D OUT

RTH = 638.7 Ω

VTH = 1.77 V

30pF* (5pF* for t HZ , t LZ , t OHZ,

t OLZ, t WZ and t OW )

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the high speed of the P4C1024L, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads

that cause supply bounce must be avoided by bringing the VCC and

ground planes directly up to the contactor fingers. A 0.01 µF high

frequency capacitor is also required between VCC and ground.

Figure 2. Thevenin Equivalent

To avoid signal reflections, proper termination must be used; for

example, a 50Ω test environment should be terminated into a 50Ω

load with 1.77V (Thevenin Voltage) at the comparator input, and a

589Ω resistor must be used in series with DOUT to match 639Ω

(Thevenin Resistance).

156

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