M312L2920BG0-A2 データシートの表示（PDF） - Samsung
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M312L2920BG0-A2 Datasheet PDF : 18 Pages
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1GB, 2GB Registered DIMM
DDR SDRAM
Parameter
Symbol
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
tDH
Control & Address input
tIPW
DQ & DM input pulse width tDIPW
Power down exit time
tPDEX
Exit self refresh to non-Read tXSNR
Exit self refresh to read com- tXSRD
Refresh interval time
tREFI
Output DQS valid window
tQH
Clock half period
tHP
Data hold skew factor
tQHS
DQS write postamble time tWPST
Active to Read with Auto pre-
charge
tRAP
command
Autoprecharge write recov-
ery +
Precharge time
tDAL
B3
(DDR333@CL=2.5))
Min
Max
12
0.45
0.45
2.2
1.75
6
75
200
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.5
0.4
0.6
18
(tWR/tCK)
+
(tRP/tCK)
A2
(DDR266@CL=2)
Min
Max
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.75
0.4
0.6
20
(tWR/tCK)
+
(tRP/tCK)
B0
(DDR266@CL=2.5)
Min
Max
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.75
0.4
0.6
20
(tWR/tCK)
+
(tRP/tCK)
Unit Note
ns
ns j, k
ns j, k
ns 8
ns 8
ns
ns
tCK
us 4
ns 11
ns 10, 11
ns 11
tCK 2
tCK 13
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure
proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
PARAMETER
SYMBOL
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
DDR333
MIN
MAX
TBD
TBD
DDR266
MIN
MAX
TBD
TBD
DDR200
MIN
MAX
0.5
4.0
Units
V/ns
Notes
a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
tIS
tIH
Units
0.5 V/ns
0
0
ps
0.4 V/ns
+50
0
ps
0.3 V/ns
+100
0
ps
Notes
i
i
i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
tDS
tDH
Units
0.5 V/ns
0
0
ps
0.4 V/ns
+75
+75
ps
0.3 V/ns
+150
+150
ps
Notes
k
k
k
Rev. 1.1 August. 2003
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