IDTCV144
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 9, LVDS CONTROL BYTE
Bit
Output(s) Affected
Description/Function
0
1
Type
0
LVDS
HW/ SMBus control
HW(1)
SW
RW
1
LVDS SSC EN
Spread spectrum enable
Off
On
RW
2
Reserved
RW
3
SEL 100/96#
Select LVDS frequency
96MHz
100MHZ
RW
4
S3
see SSC table
RW
5
S2
see SSC table
RW
6
S1
see SSC table
RW
7
S0
see SSC table
RW
NOTE:
1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.
Power On
0
1
0
SEL 100/96#
0
1
1
1
BYTE 10
Bit
0
1
2
3
4
5
6
7
Output(s) Affected
Reserved
Reserved
Reserved
Description / Function
N Programming enable
LVDS PLL power down
USB PLL power down
SRC PLL power down
CPU PLL power down
0
Disable
Normal
Normal
Normal
Normal
1
Enable
Power Down
Power Down
Power Down
PowerDown
Type
Power On
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
BYTE 11
Bit
Output(s) Affected
Description / Function
0
0
SRC SMC0
SRC/PCI SSC control
1
SRC SMC1
2
SRC SMC2
see SMC table
3
Reserved
4
CPU SMC0
CPU PLL SSC control
5
CPU SMC1
see SMC table
6
CPU SMC2
7
Reserved
BYTE 12
Bit
Output(s) Affected
Description / Function
0
0
CPU_N0, LSB
CPU CLK = N* Resolution
1
CPU_N1
see Resolution table
2
CPU_N2
3
CPU_N3
4
CPU_N4
5
CPU_N5
6
CPU_N6
7
CPU_N7, MSB
9
1
Type
Power On
RW
1
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
1
Type
Power On
RW
0
RW
1
RW
1
RW
0
RW
1
RW
0
RW
0
RW
1