IDTCV144 データシートの表示（PDF） - Integrated Device Technology
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IDTCV144 Datasheet PDF : 25 Pages
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IDTCV144
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
BYTE 13
Bit
0
1
2
3
4
5
6
7
Output(s) Affected
SRC_N0, LSB
SRC_N1
SRC_N2
SRC_N3
SRC_N4
SRC_N5
SRC_N6
SRC_N7, MSB
Description / Function
SRC f = N*SRC Resolution
Resolution = 0.666667
100MHz N= 150
BYTE 14
Bit
0
1
2
3
4
5
6
7
Output(s) Affected
48MHzStr0
48MHStr1
REFStr0
REFStr1
PCIStrC0
PCIStrC1
PCIFStr0
PCIFStr1
Description / Function
USB48MHz0 strength selection
REF strength selection
PCI strength selection
PCIF strength selection
0
0
COMMERCIAL TEMPERATURE RANGE
1
Type
Power On
RW
0
RW
1
RW
1
RW
0
RW
1
RW
0
RW
0
RW
1
1
Type
Power On
RW
1
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
BYTE 15
Bit
0
1
2
3
4
5
6
7
Output(s) Affected
PCI0
PCI1
PCI2
PCI3
Reserved
Reserved
Reserved
Reserved
Description / Function
Allow controlled by
PCI_STOP# assertion
0
Free running, not
affected by PCI_STOP#
1
Stopped with
PCI_STOP#
Type
Power On
RW
1
RW
1
RW
1
RW
1
0
0
0
0
BYTES 16 - 20 ARE NOT TO BE USED
BYTE 21(1,2)
Bit Output(s)Affected
Description / Function
0
1
Type Power On
0
LVDS
1
SRC2
2
SRC4
3
Reserved
4
SRC1
5
SRC3
6
SRC5
7
Reserved
RW
0
Controlled by CLKREQA#. When CLKREQA#
Not Controlled
Controlled
RW
0
is HIGH, output is Hi-Z
RW
1
RW
0
RW
0
Controlled by CLKREQB#. When CLKREQB#
Not Controlled
Controlled
RW
0
is HIGH, output is Hi-Z
RW
1
RW
0
NOTES:
1. When SRCCLK outputs controlled by CLKREQA# and CLKREQB# are enabled, clock output behavior will follow SMBus control bits (per CK410 spec).
2. Assertion/de-assertion time of CLKREQ# pins will match PCI_STOP# timing of the CK410 spec. This is 15ns from the assertion/de-assertion of CLKREQ# to the drive/tie-state
of the respective SRCCLK output.
10
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