IDT82V2048E データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

一致するリスト

IDT82V2048E

OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 30

3.8.2 ERROR DETECTION AND COUNTING ................................................................ 30

3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 31

3.9 LINE DRIVER FAILURE MONITORING ........................................................................... 31

3.10 MCLK AND TCLK ............................................................................................................. 32

3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 32

3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 32

3.11 MICROCONTROLLER INTERFACES ............................................................................. 33

3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 33

3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 33

3.12 INTERRUPT HANDLING .................................................................................................. 34

3.13 GENERAL PURPOSE I/O ................................................................................................ 35

3.14 5V TOLERANT I/O PINS .................................................................................................. 35

3.15 RESET OPERATION ........................................................................................................ 35

3.16 POWER SUPPLY ............................................................................................................. 35

4 PROGRAMMING INFORMATION .............................................................................................. 36

4.1 REGISTER LIST AND MAP ............................................................................................. 36

4.2 REGISTER DESCRIPTION .............................................................................................. 38

4.2.1 GLOBAL REGISTERS............................................................................................ 38

4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 40

4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 41

4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 43

4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 45

4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 48

4.2.7 LINE STATUS REGISTERS ................................................................................... 50

4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 52

4.2.9 COUNTER REGISTERS ........................................................................................ 53

4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 54

5 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 55

5.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 56

5.2 JTAG DATA REGISTER ................................................................................................... 56

5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 56

5.2.2 BYPASS REGISTER (BR)...................................................................................... 56

5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 56

5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 57

6 TEST SPECIFICATIONS ............................................................................................................ 59

7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 71

7.1 SERIAL INTERFACE TIMING .......................................................................................... 71

7.2 PARALLEL INTERFACE TIMING ..................................................................................... 72

4

Share Link: