IDT82V2048E データシートの表示（PDF） - Integrated Device Technology
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IDT82V2048E Datasheet PDF : 76 Pages
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OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
TD8/TDP8
TDN1
TDN2
TDN3
TDN4
TDN5
TDN6
TDN7
TDN8
Type
Input
Pin No.
Description
PQFP208 PBGA208
Transmit and Receive Digital Data Interface
155
B15 TDn: Transmit Data for Channel 1~8
149
D15 In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled
143
E15 into the device on the active edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL
137
G15 bit (TCF0, 02H...). Data is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted to
127
J15 the line. In this mode, TDNn should be connected to ground.
121
L15
115
N15 TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~8
109
R16 In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sam-
pled into the device on the active edge of TCLKn. The active edge of the TCLKn is selected by the
154
C14 TCLK_SEL bit (TCF0, 02H...) The line code in Dual Rail Mode is as follows:
148
D14
142
F13
TDPn TDNn
Output Pulse
136
G14
0
0 Space
126
J14
120
L14
114
M13
108
P15
0
1 Positive Pulse
1
0 Negative Pulse
1
1 Space
TCLK1
156
TCLK2
150
TCLK3
144
TCLK4
Input
138
TCLK5
129
TCLK6
122
TCLK7
116
TCLK8
110
RD1/RDP1
152
RD2/RDP2
146
RD3/RDP3
140
RD4/RDP4
134
RD5/RDP5
124
RD6/RDP6
118
RD7/RDP7
112
RD8/RDP8
106
Output
CV1/RDN1
151
CV2/RDN2
145
CV3/RDN3
139
CV4/RDN4
132
CV5/RDN5
123
CV6/RDN6
117
CV7/RDN7
111
CV8/RDN8
105
RCLK1
153
RCLK2
147
RCLK3
141
RCLK4
Output
135
RCLK5
125
RCLK6
119
RCLK7
113
RCLK8
107
A15 TCLKn: Transmit Clock for Channel 1~8
C16 These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit
E16 data on TDn/TDPn or TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is
G16 missing1 and the TCLKn missing interrupt is not masked, an interrupt will be generated.
J16
L16
N16
T16
B16 RDn: Receive Data for Channel 1~8
E14 In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI,
F15 HDB3 or B8ZS line code rules. The active level on RDn pin is selected by the RD_INV bit (RCF0,
H14 07H...).
K14
M15 CVn: Code Violation for Channel 1~8
N14 In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn
P14 to high level for a full clock cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/
HDB3 decoder is enabled. When AMI decoder is selected, the bipolar violation can be indicated.
C15
E13 RDPn/RDNn: Positive/Negative Receive Data for Channel 1~8
F14 In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recov-
H13 ered clock. An active level on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while
K13 an active level on RDNn indicates the receipt of a negative pulse on RTIPn/RRINGn. The active level
M14 on RDPn/RDNn is selected by the RD_INV bit (RCF0, 07H...). When CDR is disabled, these pins
N13 directly output the raw RZ sliced data. The output data on RDn and RDPn/RDNn is updated on the
R15 active edge of RCLKn.
A16 RCLKn: Receive Clock for Channel 1~8
D16 These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS
F16 conditions, if AISE bit (MAINT0, 0AH...) is ‘1’, RCLKn is derived from MCLK.
H15 In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/
K15 RRINGn. The receive data (RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on
M16 the active edge of RCLKn. The active edge is selected by the RCLK_SEL bit (RCF0, 07H...).
P16 If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data
T15 RDPn and RDNn. This signal can be used in the applications with external clock recovery circuitry.
Notes:
1. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles.
11
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