IDT71V124S15 データシートの表示（PDF） - Integrated Device Technology

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IDT71V124S15

3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Integrated Device Technology 

IDT71V124, 3.3V CMOS Static RAM

1 Meg (128K x 8-Bit), Revolutionary Pinout

Timing Waveform of Read Cycle No. 1(1)

Commercial and Industrial Temperature Ranges

ADDRESS

tRC

tAA

OE

tOE

CS

tOLZ (5)

tACS (3)

DATAOUT

N CE VCC SUPPLY ICC

CURRENT ISB

tCLZ (5)

HIGH IMPEDANCE

tPU

tOHZ (5)

tCHZ (5)

DATAOUT VALID

tPD

RT I CEN24SANS Timing Waveform of Read Cycle No. 2(1,2,4)

PA ES V1 IG ADDRESS

L 71 DES DATAOUT

tRC

tAA

tOH

PREVIOUS DATAOUT VALID

tOH

DATAOUT VALID

SO ER W NOTES:

1. WE is HIGH for Read Cycle.

D E 2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

B R N 4. OE is LOW.

O OFOR 5. Transition is measured ±200mV from steady state.

3484 drw 05

3484 drw 06

6.542

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