IDT71V124S15 データシートの表示（PDF） - Integrated Device Technology

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IDT71V124S15

3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Integrated Device Technology 

3.3V CMOS Static RAM

1 Meg (128K x 8-Bit)

Revolutionary Pinout

IDT71V124

Features

Description

◆ 128K x 8 advanced high-speed CMOS static RAM

The IDT71V124 is a 1,048,576-bit high-speed static RAM orga-

◆ JEDEC revolutionary pinout (center power/GND) for

nized as 128K x 8. It is fabricated using IDT’s high-performance, high-

reduced noise

reliability CMOS technology. This state-of-the-art technology, com-

◆ Commercial (0°C to +70°C) and Industrial (–40°C to

bined with innovative circuit design techniques, provides a cost-

+85°C) temperature options

effective solution for high-speed memory needs. The JEDEC center

◆ Equal access and cycle times

power/GND pinout reduces noise generation and improves system

— Industrial and Commercial: 15/20ns

performance.

◆ One Chip Select plus one Output Enable pin

◆ Bidirectional inputs and outputs directly

LVTTL-compatible

E ◆ Low power consumption via chip deselect

◆ Available in 32-pin 400 mil Plastic SOJ.

IN NC Functional Block Diagram

The IDT71V124 has an output enable pin which operates as fast as

7ns, with address access times as fast as 15ns available. All bidirec-

tional inputs and outputs of the IDT71V124 are LVTTL-compatible and

operation is from a single 3.3V supply. Fully static asynchronous

circuitry is used; no clocks or refreshes are required for operation.

The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ.

RT CE 24SANS A0

A S 1 G •

•

I •

ADDRESS

•

P E V S •

•

L 1 E DECODER

7 A16

1,048,576-BIT

MEMORY ARRAY

OBSOOFRODRERNEW D I/O0 -I/O7

8

8

8

I/O CONTROL

WE

OE

CS

©2000 Integrated Device Technology, Inc.

CONTROL

LOGIC

1

3484 drw 01

AUGUST 2000

DSC-3484/05

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