ICS570AT(2000) データシートの表示（PDF） - Integrated Circuit Systems

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ICS570AT
(Rev.:2000)

Multiplier and Zero Delay Buffer

Integrated Circuit Systems 

ICS570A

Multiplier and Zero Delay Buffer

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Referenced to GND

Inputs

Referenced to GND

Clock Output

Referenced to GND

Ambient Operating Temperature

ICS570M

ICS570MI

Soldering Temperature

Max of 10 seconds

Storage temperature

DC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted)

Operating Voltage, VDD

Input High Voltage, VIH, VDD=5V

ICLK, FBIN

Input Low Voltage, VIL, VDD=5V

ICLK, FBIN

Input High Voltage, VIH

S0, S1

Input High Voltage, VIM (mid-level)

S0, S1

Input Low Voltage, VIL

S0, S1

Output High Voltage, VOH, CMOS level

IOH=-4mA

Output High Voltage, VOH

IOH=-12mA

Output Low Voltage, VOL

IOL=12mA

IDD Operating Supply Current, 50 in, 100 out No Load, 5.0V

IDD Operating Supply Current, 50 in, 100 out No Load, 3.3V

Short Circuit Current

Each Output

Input Capacitance, S1, S0

AC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted)

Input Frequency, ICLK (see table on page 2)

Output Clock Frequency, CLK

Skew of output clocks

Note 2

Input skew, ICLK to FBIN Note 2

VDD=3.3V, CLK>10MHz

Input skew, ICLK to FBIN Note 2

VDD=3.3V, CLK<5MHz

Input skew, ICLK to FBIN Note 2

VDD=3.3V, CLK<10MHz

Input skew, ICLK to FBIN Note 2

VDD=5V, CLK<10MHz

Input skew, ICLK to FBIN Note 2

VDD=5V, CLK>10MHz

Output Clock Rise Time, 3.3V

0.8 to 2.0V, note 3

Output Clock Fall Time, 3.3V

2.0 to 0.8V, note 3

Output Clock Rise Time, 5V

0.8 to 2.0V, note 3

Output Clock Fall Time, 5V

2.0 to 0.8V, note 3

Output Clock Duty Cycle

at VDD/2

Minimum

-0.5

-0.5

0

-40

-65

3

2

VDD-0.5

VDD-0.4

2.4

2.5

10

-500

-1.0

-750

-1.5

-1.0

45

Notes

1. Stresses beyond these can permanently damage the device

2. Assumes clocks with same rise time, measured from rising edges at VDD/2.

3. With 27 Ω terminating resistor and 15 pF loads.

Typical Maximum

7

VDD+0.5

VDD+0.5

70

85

260

150

5.5

0.8

VDD/2

0.5

0.4

22

12

±50

5

150

150

50

150

500

1.0

750

1.5

1.0

0.75

0.75

0.5

0.5

49 to 51

55

Units

V

V

V

°C

°C

°C

°C

V

V

V

V

V

V

V

V

V

mA

mA

mA

pF

MHz

MHz

ps

ps

ns

ps

ns

ns

ns

ns

ns

ns

%

MDS 570A C

3

Revision 102700

Printed 11/14/00

Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com

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