ICS570AT(2000) データシートの表示（PDF） - Integrated Circuit Systems
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ICS570AT Datasheet PDF : 6 Pages
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ICS570A
Multiplier and Zero Delay Buffer
Pin Assignment
Clock Multiplier Decoding Table
(Multiplies input clock by shown amount)
S1
VDD
GND
ICLK
1
8
2
7
3
6
4
5
8 pin SOIC
CLK/2
CLK
S0
FBIN
FBIN from CLK FBIN from CLK/2 ICLK Input Range
S1 S0 CLK CLK/2 CLK CLK/2 FB from CLK/2 *
#1 #6 pin # 7 pin # 8 pin # 7 pin # 8
(3.3V, MHz)
00
Power Down and Tri-State
-
0 M x3
x1.5
x6
x3
2.5 to 25
01
x4
x2
x8
x4
2.5 to 19
M0
x8
x4
x16
x8
2.5 to 9.5
M M x6
x3
x12
x6
2.5 to 12.5
M 1 x10
x5
x20
x10
2.5 to 7.5
10
x1
÷2
x2
x1
5 to 75
1 M x16
x8
x32
x16
2.5 to 5
11
x2
x1
x4
x2
2.5 to 37.5
0 = connect directly to ground.
M = leave unconnected (self-biases to VDD/2).
1 = connect directly to VDD.
*Input range with CLK feedback is double that for CLK/2.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
S1
VDD
GND
ICLK
FBIN
S0
CLK
CLK/2
Type
I
P
P
CI
CI
I
O
O
Description
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
Connect to +3.3V or +5V.
Connect to ground.
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
Clock output per Table above.
Clock output per Table above. Low skew divide by two of pin 7 clock.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS570A requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must
be connected close to the ICS570A to minimize lead inductance. No external power supply filtering is
required for this device. A 27 Ω terminating resistor can be used next to each output pin.
MDS 570A C
2
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
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