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AN-6920MR

Integrated Critical-Mode PFC / Quasi-Resonant Current-Mode PWM Controller FAN6920

Fairchild Semiconductor 

AN-6920

By increasing VRO (i.e. the turns ratio, n), the capacitive

switching loss and conduction loss of the MOSFET are

reduced. This also reduces the voltage stress of the

secondary-side rectifier. VRO should be determined by a

trade-off between the hold-up time and voltage stresses of

the secondary-side rectifier diode.

APPLICATION NOTE

output capacitor effects the hold-up time. The minimum

PFC output voltage for required hold-up time is obtained as:

V ≥ min

O.PFC

where:

2 ⋅ t HOLD ⋅ POUT

η ⋅ CO.PFC

+V 2

O.PFC.HLD

(18)

tHOLD is the required holdup time;

POUT is total nominal output power;

VO.PFC.L is the minimum PFC output voltage for required

hold-up time; and

VO.PFC.HLD is the allowable minimum PFC output voltage

during the hold-up time.

The voltage of transformer primary-side winding is clamped

to VO,PFC, so the minimum PFC output voltage during the

hold-up time is obtained as:

VO.PFC.HLD = n ⋅ (VO + VF )

(19)

where VF is the synchronous rectification MOSFET drain-

to-source diode forward voltage, VF, about 1V.

(Design Example) Because the PFC response is very slow,

the hold-up time needs to be more than 12ms to avoid PFC

output voltage drop effecting the output voltage at

dynamic-load condition. Assuming hold-up time is 12ms,

the VO.PFCmin as:

V ≥ min

O.PFC

2 ⋅ tHOLD ⋅ POUT

η ⋅ CO.PFC

+ [n ⋅ (VO

+ VF )]2

= 2 ⋅12 ×10−3 × 90 + [12 ⋅ (19 + 1)]2 = 286V

0.9 ⋅100 ×10−6

Figure 13.Typical Waveforms of QR Flyback Converter

(Design Example) Assuming 75V MOSFET

(synchronous rectification) is used for secondary side,

with 70% voltage margin:

0.7 ⋅ 75 > VD nom

= VO

+

VO.PFC

n

∴n > VO.PFC = 400 = 11.94

0.7 ⋅ 75 − VO 0.7 ⋅ 75 − 19

Thus, n is determined as 12.

[STEP-B2] Calculate the Minimum PFC Output

Voltage (VO.PFC.L) for Hold-up Time

For the PFC output capacitor, it is typical to use 0.5~1µF

per 1W output power for 400V PFC output. Meanwhile, it is

reasonable to use ~1µF per 1W output power for variable

output PFC due to the larger voltage drop during the hold-

up time than 400V output. In this example, two 100µF

capacitors are selected for the output capacitors (CO.PFC).

Lower PFC output voltage can improve system efficiency at

low AC line voltage condition, but the energy of the PFC

[STEP-B3] Transformer Design

Figure 14 shows the typical switching timing of a quasi-

resonant converter. The sum of MOSFET conduction time

(tON), diode conduction time (tD), and drain voltage falling

time (tF) is the switching period (tS). To determine the

primary-side inductance (Lm), the following parameters

should be determined first.

Minimum Switching Frequency (fS.QRmin)

The minimum switching frequency occurs at the minimum

input voltage and full-load condition, which should be

higher than 20kHz to avoid audible noise. By increasing

fS.QRmin, the transformer size can be reduced. However, this

results in increased switching losses. Determine fS.QRmin by a

trade-off between switching losses and transformer size.

Typically fS.QRmin is set around 70kHz.

Falling Time of the MOSFET Drain Voltage (tF)

As shown in Figure 14, the MOSFET drain voltage fall time

is half of the resonant period of the MOSFET’s effective

output capacitance and primary-side inductance. The typical

value for tF is 0.6~1.2µs.

© 2010 Fairchild Semiconductor Corporation

Rev. 1.0.0 • March 10, 2011

8

www.fairchildsemi.com

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