AN-6920MR データシートの表示（PDF） - Fairchild Semiconductor
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AN-6920MR
Fairchild Semiconductor
AN-6920MR Datasheet PDF : 17 Pages
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AN-6920
The output is indirectly monitored for over-voltage
protection using the DET pin voltage while the MOSFET is
turned off. The ratio of RDET1 and RDET2 should be
determined as:
2.5 =
RDET 2
RDET 1 + RDET 2
N
N
A
S
VOVP
=
1
K DET
+
1
NA
NS
VOVP
(31)
where the ratio between RDET1 and RDET2 is obtained as:
K DET
=
RDET 1
RDET 2
=
NA
NS
⋅ VOVP
2. 5
−1
(32)
For a quasi-resonant flyback converter, the peak-drain
current with a given output power decreases as input voltage
increases. Thus, constant power limit cannot be achieved by
using pulse-by-pulse current limit with constant threshold.
FAN6920 has high/low line over-power compensation that
reduces the pulse-by-pulse current limit level as input
voltage increases. FAN6920 senses the input voltage using
the current flowing out of the DET pin while the MOSFET
is turned on. The pulse-by-pulse current limit level vs. DET
current is depicted in Figure 18.
The DET pin current for low-line and high-line PFC output
voltages are given as:
I DET .L
=
VO.PFC.L
NA
NP
RDET 1
− 0.7
+
0. 7
RDET 2
≅
VO.PFC.L
NA
NP
RDET 1
I DET .H
VO. PFC . H
=
NA
NP
RDET 1
− 0.7
+
0. 7
RDET 2
VO. PFC . H
≅
NA
NP
RDET 1
(33)
(34)
Figure 17. Switching Frequency and Peak-Drain
Current Change as Input Voltage Increases
APPLICATION NOTE
Figure 18. IDET-VLIMIT Curve
The relationship between IDET and VLIMIT in the linear region
(IDET=100~500µA) can be approximated as:
VLIMIT = −877 ⋅ IDET + 0.882
(35)
Assuming two-level voltage PFC output: for a given output
power, the ratio between drain-peak currents at low line and
high line is obtained as:
I PK .L
DS
= VO.PFC .H
⋅ VO.PFC.L + VRO
I PK .H
DS
V V + V O.PFC.L O.PFC .H
RO
(36)
For a given output power, the ratio between pulse-by-pulse
current limit levels at low line and high line is obtained as:
VLIMIT .L
≅
−994 ⋅VO.PFC.L
NA
NP
+
RDET 1
VLIMIT .H
−994 ⋅VO.PFC.H
NA
NP
+ RDET1
(37)
To get a constant power limit, RDET1 should be determined
such that Equations (38) and (39) are equal. However, for
actual design, it is typical to use 108~115% of Equation
(38), considering the pulse-by-pulse turn-off delay and
increased PFC output voltage ripple at low line.
Once the current-limit threshold voltage is determined with
RDET1, the current-sensing resistor value is obtained as:
VLIMIT
VO . PFC . L
= −877 ⋅ (
NA
NP
RDET 1
− 0.7
+
0.7
) + 0.882
RDET 2
(38)
The current-sensing resistor value can be obtained from:
RCS 2
=
VLIMIT
I LIM
DS
(39)
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
11
www.fairchildsemi.com
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