DS2148 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2148

5V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

LOOP BACK CONTROL IN HARDWARE MODE Table 4-5

LOOPBACK

SYMBOL CONTROL BIT

LOOP1

Remote Loop Back

RLB

CCR6.6

1

Local Loop Back

LLB

CCR6.7

1

Analog Loop Back

ALB

CCR6.4

0

No Loop Back

–

–

0

DS2148/Q48

LOOP0

1

0

1

0

TRANSMIT DATA CONTROL IN HARDWARE MODE Table 4-6

TRANSMIT DATA

SYMBOL

CONTROL BIT

TX1

TX0

Transmit Unframed All Ones

TUA1

CCR3.7

1

1

Transmit Alternating Ones and

TAOZ

CCR3.5

1

0

Zeros

Transmit PRBS

TPRBSE

CCR3.4

0

1

TPOS and TNEG

–

–

0

0

RECEIVE SENSITIVITY SETTINGS Table 4-7

EGL

(CCR4.4)

ETS

(CCR1.7)

RECEIVE SENSITIVITY

0

0 (E1)

-12dB (short haul)

1

0 (E1)

-43dB (long haul)

1

1 (T1)

-30dB (limited long haul)

0

1 (T1)

-36dB (long haul)

MONITOR GAIN SETTINGS Table 4-8

MM1

MM0

(CCR5.5)

(CCR5.4)

0

0

0

1

1

0

1

1

INTERNAL LINEAR GAIN

BOOST (dB)

Normal operation (no boost)

20

26

32

INTERNAL RX TERMINATION SELECT Table 4-9

RT1

RT0

INTERNAL RECEIVE

(CCR5.1)

(CCR5.0)

TERMINATION CONFIGURATION

0

0

Internal receive-side termination disabled

0

1

Internal receive-side 120W enabled

1

0

Internal receive-side 100W enabled

1

1

Internal receive-side 75W enabled

MCLK SELECTION Table 4-10

MCLK

JAMUX

(CCR1.3)

2.048MHz

0

2.048MHz

1

1.544MHz

0

ETS

(CCR1.7)

0

1

1

20 of 75

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