DS2148 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2148

5V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

ACRONYM PIN

RNEG

39

RPOS

38

RTIP/

27/

RRING

28

SCLK

5

SDI

6

SDO

7

TCLK

43

TEST

26

TNEG

42

TPOS

41

TTIP/

34/

TRING

37

VDD

21/

36

VSM

20

VSS

22/

35

I/O DESCRIPTION

DS2148/Q48

O Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)

or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out

of the line interface. Set NRZE (CCR1.6) to a one for NRZ

applications. In NRZ mode, data will be output on RPOS while a

received error will cause a positive-going pulse synchronous with

RCLK at RNEG. See section 8.4 for details.

O Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or

the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the

line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In

NRZ mode, data will be output on RPOS while a received error will

cause a positive-going pulse synchronous with RCLK at RNEG. See

section 8.4 for details.

I Receive Tip and Ring. Analog inputs for clock recovery circuitry.

These pins connect via a 1:1 transformer to the line. See Section 7

for details.

I Serial Clock. Serial bus clock input.

I Serial Data Input. Sampled on rising edge (ICES = 0) or the falling

edge (ICES = 1) of SCLK.

O Serial Data Output. Valid on the falling edge (OCES = 0) or the

rising edge (OCES = 1) of SCLK.

I Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used

to clock data through the transmit side formatter. Can be sourced

internally by MCLK or RCLK. See Common Control Register 1 and

Figure 3-3.

I 3-State Control. Set high to 3-state all outputs and I/O pins

(including the parallel control port). Set low for normal operation.

Useful in board level testing.

I Transmit Negative Data. Sampled on the falling edge (CCR2.1 =

0) or the rising edge (CCR2.1 = 1) of TCLK for data to be

transmitted out onto the line.

I Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)

or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted

out onto the line.

O Transmit Tip and Ring [TTIP & TRING]. Analog line driver

outputs. These pins connect via a step-up transformer to the line. See

Section 7 for details.

- Positive Supply. 5.0V ±5%

I Voltage Supply Mode. Should be tied high for 5V operation

- Signal Ground.

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