DM9103 データシートの表示（PDF） - Davicom Semiconductor, Inc.

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DM9103

10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface

Davicom Semiconductor, Inc. 

19:10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

1

1

0

1

DM9103

3-port switch with PCI Interface

RO

Reserved

RO

Master Mode Fast Back-To-Back (0 for No Support)

The DM9103 does not support master mode fast back-to-back capability

and will not generate fast back-to-back cycles

RW

SERR# Driver Enable/Disable

This bit controls the assertion of SERR# signal output. The SERR# output

will be asserted on detection of an address parity error and if both this bit

and bit 6 are set

RO

Address/Data Stepping (0 for No Stepping)

RW

Parity Error Response Enable/Disable

Setting this bit will enable the DM9103 to assert PERR# on the detection

of a data parity error and to assert SERR# for reporting address parity

error

RO

VGA Palette Snooping (0 for No Support)

RO

Memory Write and Invalid (0 for No Implementation)

The DM9103 only generates memory write cycle

RO

Special Cycles (0 for No Implementation)

RW

Master Device Capability Enable/Disable

When this bit is set, DM9103 has the ability of master mode operation

RW

Memory Space Access Enable/Disable

This bit controls the ability of memory space access. The memory access

includes memory mapped I/O access and Boot ROM access. As the

system boots up, this bit will be enabled by BIOS for Boot ROM memory

access. While in normal operation, using memory mapped I/O access,

this bit should be set by driver before memory access cycles

RW

I/O Space Access Enable/Disable

This bit controls the ability of I/O space access. It will be set by BIOS after

power on

6.1.3 Revision ID (xxxxxx08H - PCIRV)

Bit

Default

31:8 020000H

7:4

0001

3:0

0000

Type

RO

RO

RO

Description

Class Code (020000H)

This is the standard code for Ethernet LAN controller

Revision Major Number

This is the silicon-major revision number that will increase for the subsequent

versions of the DM9103

Revision Minor Number

This is the silicon-minor revision number that will increase for the subsequent

versions of the DM9103

Preliminary datasheet

19

DM9103-DS-P02

September 26, 2007

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