DM9103 データシートの表示（PDF） - Davicom Semiconductor, Inc.
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DM9103 Datasheet PDF : 89 Pages
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DM9103
3-port switch with PCI Interface
6.1.1 Identification ID (xxxxxx00H - PCIID)
Bit
16:31
0:15
Default
9013H
1282H
Type
RO
RO
Description
The field identifies the particular device. Unique and fixed number for the DM9103
is 9013H.
This field identifies the manufacturer of the device. Unique and fixed number for
Davicom is 1282H.
6.1.2 Command & Status (xxxxxx04H - PCICS)
Bit
Default
31
0
30
0
29
0
28
0
27
0
26:25
01
24
0
23
0
22
0
21
0
20
1
18
Type
R/C
R/C
R/C
R/C
R/C
R/C
R/C
RO
RO
RO
RO
Description
Detected Parity Error
The DM9103 samples the AD[0:31], C/BE[0:3]#, and the PAR signal to
check parity and to set parity errors. In slave mode, the parity check falls
on command phase and data valid phase (IRDY# and TRDY# both
active). In master mode, the DM9103 will check each data phase, during
a memory read cycle, for parity error. During a memory write cycle, if an
error occurs, the PERR# signal will be driven by the target. This bit is set
by the DM9103 and cleared by writing "1". There is no effect by writing "0"
Signal For System Error
This bit is set when the SERR# signal is driven by the DM9103. This
system error occurs when an address parity is detected under the
condition that bit 8 and bit 6 in command register below are set
Master Abort Detected
This bit is set when the DM9103 terminates a master cycle with the
master-abort bus transaction
Target Abort Detected
This bit is set when the DM9103 terminates a master cycle due to a
target-abort signal from other targets
Send Target Abort (0 for No Implementation)
The DM9103 will never assert the target-abort sequence
DEVSEL Timing (01 Select Medium Timing)
Medium timing of DEVSEL# means the DM9103 will assert DEVSEL#
signal two clocks after FRAME# is sample “asserted”
Data Parity Error Detected
This bit will take effect only when operating as a master and when a Parity
Error Response Bit in command configuration register is set. It is set under
two conditions:
(i) PERR# asserted by the DM9103 in memory data read error
(ii) PERR# sent from the target due to memory data write error
Slave Mode Fast Back-To-Back Capable (0 for No Support)
This bit is always reads "1" to indicate that the DM9103 is capable of
accepting fast back-to-back transaction as a slave mode device
User-Definable Feature Supported (0 for No Support)
66 MHz (0 for No Capability)
New Capability
This bit indicates whether this function implements a list of extended
capabilities.
Preliminary datasheet
DM9103-DS-P02
September 26, 2007
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