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DM9103 データシートの表示(PDF) - Davicom Semiconductor, Inc.

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DM9103 Datasheet PDF : 89 Pages
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DM9103
3-port switch with PCI Interface
5.9 Strap pins table
1: pull-high 1K~10K, 0: default floating.
5.9.1 Strap pin in 3-port mode
Pin No.
Pin Name Description
52
50
58
59
60,51
61
EECS
EEDO
TXD2_3
TXD2_2
TXD2_1,EECK
TXD2_0
Source of System Clock
0: system clock is internal 50MHz clock
1: use SCLK pin as system clock
When Port 2 in force status mode
0: Port 2 in 100Mbps
1: Port 2 in 10Mbps
When Port 2 in force status mode
0: link ON
1: link OFF
0: Port 2 status from external PHY
1: Port 2 status in force mode
00: Port 2 is MII mode (Default)
01: Port 2 is in reverse MII mode
10: Port 2 is in RMII mode and memory BIST disabled
11: Port 2 is in RMII mode
When Port 2 in force status mod
0: Port 2 in full duplex mode
1: Port 2 I half duplex mode
5.9.2 strap pin in 2-port mode
Pin No. Pin Name Description
52
50
58
59
60,51
61
63
EECS
EEDO
TXD2_3
TXD2_2
TXD2_1,EECK
TXD2_0
TXEN2
Source of System Clock
0: system clock is internal 50MHz clock
1: use SCLK pin as system clock
When Port 2 in force status mode
0: Port 2 in 100Mbps
1: Port 2 in 10Mbps
When Port 2 in force status mode
0: link ON
1: link OFF
0: Port 2 status from external PHY
1: Port 2 status in force mode
00: Port 2 is MII mode (Default)
01: Port 2 is in reverse MII mode
10: Port 2 is in RMII mode and memory BIST disabled
11: Port 2 is in RMII mode
When Port 2 in force status mod
0: Port 2 in full duplex mode
1: Port 2 I half duplex mode
0: port 2 disabled
1: port 1 disabled
16
Preliminary datasheet
DM9103-DS-P02
September 26, 2007

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