ADSP-21161NKCAZ100 データシートの表示（PDF） - Analog Devices

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ADSP-21161NKCAZ100

SHARC Processor

Analog Devices 

PACKAGE INFORMATION

The information presented in Figure 7 provides details about

how to read the package brand and relate it to specific product

features.

a

ADSP-21161N

tppZ-cc

vvvvvv.x n.n

#yyww country_of_origin

S

Figure 7. Typical Package Brand

Table 5. Package Brand Information

Brand Key

ADSP-21161N

t

pp

z

vvvvv.x

n.n

#

yyww

Field Description

Model Number

Temperature Range

Package Type

RoHS Compliance Option

Assembly Lot Code

Silicon Revision

RoHS Compliance Designation

Date Code

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 6 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 6. Absolute Maximum Ratings

Parameter

Internal (Core) Supply Voltage (VDDINT)

Analog (PLL) Supply Voltage (AVDD)

External (I/O) Supply Voltage (VDDEXT)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Rating

–0.3 V to +2.2 V

–0.3 V to +2.2 V

–0.3 V to +4.6 V

–0.5 V to VDDEXT + 0.5 V

–0.5 V to VDDEXT + 0.5 V

200 pF

–65C to +150C

ESD CAUTION

ADSP-21161N

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS

The ADSP-21161N’s internal clock switches at higher frequen-

cies than the system input clock (CLKIN). To generate the

internal clock, the DSP uses an internal phase-locked loop

(PLL). This PLL-based clocking minimizes the skew between

the system clock (CLKIN) signal and the DSP’s internal clock

(the clock source for the external port logic and I/O pads).

The ADSP-21161N’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, link ports, serial ports, and external port (as required for

read/write strobes in asynchronous access mode). During reset,

program the ratio between the DSP’s internal clock frequency

and external (CLKIN) clock frequency with the CLK_CFG1–0

and CLKDBL pins. Even though the internal clock is the clock

source for the external port, it behaves as described in the Clock

Rate Ratio chart in Table 3 on Page 16. To determine switching

frequencies for the serial and link ports, divide down the inter-

nal clock, using the programmable divider control of each port

(DIVx for the serial ports and LxCLKD for the link ports).

Note the following definitions of various clock periods that are a

function of CLKIN and the appropriate ratio control (Table 7).

Figure 8 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and

8:1 with external oscillator or crystal. It also shows support for

CLKOUT-to-CLKIN ratios of 1:1 and 2:1.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times.

See Figure 37 on Page 54 under Test Conditions for voltage ref-

erence levels.

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given circum-

stance. Use switching characteristics to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Rev. C | Page 19 of 60 | January 2013

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