ADSP-21161NKCAZ100 データシートの表示（PDF） - Analog Devices
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ADSP-21161NKCAZ100 Datasheet PDF : 60 Pages
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ADSP-21161N
Table 8. Operation Types Versus Input Current
Operation
Instruction Type
Peak Activity1 (IDDINPEAK)
Multifunction
High Activity1 (IDDINHIGH)
Multifunction
Low Activity1 (IDDINLOW)
Single Function
Instruction Fetch
Core Memory Access2
Internal Memory DMA
External Memory DMA
Cache
2 per tCK cycle (DM64 and PM64)
1 per 2 tCCLK cycles
1 per external port cycle (32)
Internal Memory
1 per tCK cycle (DM64)
1 per 2 tCCLK cycles
1 per external port cycle (32)
Internal Memory
None
N/A
N/A
Data bit pattern for core
memory access and DMA
Worst case
Random
N/A
1 The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
2 These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on Page 19.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• The number of output pins that switch during each cycle
(O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (VDD)
and is calculated by:
PEXT = O C VDD2 f
• The bus cycle time is 55 MHz
• The external SDRAM clock rate is 110 MHz
• Ignoring SDRAM refresh cycles
• Addresses are incremental and on the same page
The PEXT equation is calculated for each class of pins that can
drive, as shown in Table 9.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
PTOTAL = PEXT + PINT + PPLL
The load capacitance should include the processor package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. At a maximum rate of 1/tCK,
address and data pins can drive high and low, while writing to a
SDRAM memory.
Example: Estimate PEXT with the following assumptions:
• A system with one bank of external memory (32 bit)
• Two 1M ؋ 16 SDRAM chips are used, each with a load of
10 pF (ignoring trace capacitance)
• External Data Memory writes can occur every cycle at a
rate of 1/tCK with 50% of the pins switching
Where:
PEXT is from Table 9.
PINT is IDDINT × 1.8 V, using the calculation IDDINT listed in Power
Dissipation on Page 20.
PPLL is AIDD × 1.8 V, using the value for AIDD listed in the Electri-
cal Characteristics on Page 18.
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Table 9. External Power Calculations—110 MHz Instruction Rate
Pin Type
Address
MSx
SDWE
Data
SDCLK0
Number of Pins
11
4
1
32
1
% Switching
20
0
0
50
100
؋C
24.7 pF
24.7 pF
24.7 pF
14.7 pF
24.7 pF
؋f
55 MHz
N/A
N/A
55 MHz
110 MHz
؋ VDD2
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
= PEXT
= 0.033 W
= 0.000 W
= 0.000 W
= 0.141 W
= 0.030 W
PEXT = 0.204 W
Rev. C | Page 21 of 60 | January 2013
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