ADSP-21161N
Table 3. Clock Rate Ratios
CLKDBL
1
1
1
0
0
0
CLK_CFG1
0
0
1
0
0
1
CLK_CFG0
0
1
0
0
1
0
Core:CLKIN
2:1
3:1
4:1
4:1
6:1
8:1
BOOT MODES
Table 4. Boot Mode Selection
EBOOT
1
0
0
0
0
1
LBOOT
0
0
1
1
0
1
BMS
Output
1 (Input)
0 (Input)
1 (Input)
0 (Input)
x (Input)
Booting Mode
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Serial Boot via SPI
Link Port
No Booting. Processor executes from external memory.
Reserved
CLKIN:CLKOUT
1:1
1
1
1:2
1:2
1:2
Rev. C | Page 16 of 60 | January 2013