ADIS16229AMLZ データシートの表示（PDF） - Analog Devices
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ADIS16229AMLZ Datasheet PDF : 37 Pages
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Preliminary Technical Data
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tCS
tDAV
tDSU
tDHD
tSR
tSF
tDF, tDR
tSFS
Description
SCLK frequency
Stall period between data, between 16th and 17th SCLK
Chip select to SCLK edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise time
SCLK fall time
DOUT rise/fall times
CS high after SCLK edge
1 Guaranteed by design, not tested.
Timing Diagrams
ADIS16000/ADIS16229
Min1
Typ
Max
Unit
0.01
2.5
MHz
25
μs
48.8
ns
100
ns
24.4
ns
48.8
ns
12.5
ns
12.5
ns
5
12.5
ns
5
ns
CS
SCLK
DOUT
DIN
tCS
1
MSB
R/W
tSR
tSF
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6
A5
A4
A3
A2
Figure 2. SPI Timing and Sequence
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
CS
SCLK
tSTALL
Figure 3. DIN Bit Sequence
Rev. PrA | Page 5 of 37
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