SST31LF021 データシートの表示（PDF） - Silicon Storage Technology

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SST31LF021

2 Mbit Flash + 1 Mbit SRAM ComboMemory

Silicon Storage Technology 

2 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF021 / SST31LF021E

EOL Data Sheet

Flash Data# Polling (DQ7)

When the SST31LF021/021E flash memory bank is in the

internal Program operation, any attempt to read DQ7 will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ7 will produce true data.

Note that even though DQ7 may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles after an interval of 1 µs. During inter-

nal Erase operation, any attempt to read DQ7 will produce

a ‘0’. Once the internal Erase operation is completed, DQ7

will produce a ‘1’. The Data# Polling is valid after the rising

edge of the fourth WE# (or BEF#) pulse for Program opera-

tion. For Sector or Bank-Erase, the Data# Polling is valid

after the rising edge of the sixth WE# (or BEF#) pulse. See

Figure 7 for Data# Polling timing diagram and Figure 17 for

a flowchart.

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The flash memory bank is then ready for the next

operation. The Toggle Bit is valid after the rising edge of the

fourth WE# (or BE#) pulse for Program operation. For Sec-

tor or Bank-Erase, the Toggle Bit is valid after the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 8 for

Toggle Bit timing diagram and Figure 17 for a flowchart.

Flash Memory Data Protection

The SST31LF021/021E flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadvertent writes.

Flash Software Data Protection (SDP)

The SST31LF021/021E provide the JEDEC approved

Software Data Protection scheme for all flash memory

bank data alteration operations, i.e., Program and Erase.

Any Program operation requires the inclusion of a series of

three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST31LF021/021E devices are shipped with the Software

Data Protection permanently enabled. See Table 4 for the

specific software command codes. During SDP command

sequence, invalid SDP commands will abort the device to

the Read mode, within TRC.

Concurrent Read and Write Operations

The SST31LF021/021E provide the unique benefit of

being able to read from or write to SRAM, while simulta-

neously erasing or programming the flash. The device will

ignore all SDP commands when an Erase or Program

operation is in progress. This allows data alteration code to

be executed from SRAM, while altering the data in flash.

The following table lists all valid states. SST does not rec-

ommend that both bank enables, BEF# and BES#, be

simultaneously asserted.

CONCURRENT READ/WRITE STATE TABLE

Flash

Program/Erase

Program/Erase

SRAM

Read

Write

Note that Product Identification commands use SDP;

therefore, these commands will also be ignored while an

Erase or Program operation is in progress.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

©2007 Silicon Storage Technology, Inc.

4

S71137-06-EOL

05/07

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