MT28S4M16LCTG-10 データシートの表示（PDF） - Micron Technology

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MT28S4M16LCTG-10

SYNCFLASH® MEMORY

Micron Technology 

GENERAL DESCRIPTION (continued)

also available when VHH is applied to the RP# pin. Pro-

gramming or erasing the device is done with a 3.3V

VCCP voltage, while all other operations are performed

with a 3.3V VCC. The device is fabricated with Micron’s

advanced CMOS floating-gate process.

The MT28S4M16LC is organized into 16 indepen-

dently erasable blocks. To ensure that critical firmware

is protected from accidental erasure or overwrite, the

MT28S4M16LC features sixteen 256K-word hardware-

and software-lockable blocks.

The MT28S4M16LC four-bank architecture supports

true concurrent operations. A read access to any bank

can occur simultaneously with a background PRO-

GRAM or ERASE operation to any other bank.

The SyncFlash memory has a synchronous inter-

face (all signals are registered on the positive edge of

the clock signal, CLK). Read accesses to the memory are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the regis-

tration of an ACTIVE command, followed by a READ

command. The address bits registered coincident with

the ACTIVE command are used to select the bank and

4 MEG x 16

SYNCFLASH MEMORY

row to be accessed. The address bits registered coinci-

dent with the READ command are used to select the

starting column location for the burst access.

The SyncFlash memory provides for programmable

read burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a burst terminate option.

The 4 Meg x 16 SyncFlash memory uses an internal

pipelined architecture to achieve high-speed

operation.

The 4 Meg x 16 SyncFlash memory is designed to

operate in 3.3V, low-power memory systems. A deep

power-down mode is provided, along with a power-

saving standby mode. All inputs and outputs are

LVTTL-compatible.

SyncFlash memory offers substantial advances in

Flash operating performance, including the ability to

synchronously burst data at a high data rate with auto-

matic column-address generation and the capability

to randomly change column addresses on each clock

cycle during a burst access.

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

4 Meg x 16 SyncFlash

MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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