HSP45106 データシートの表示（PDF） - Intersil
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HSP45106 Datasheet PDF : 14 Pages
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HSP45106
The timing for loading the Center Frequency Register (MSB
and LSB) and data being output on COS(15:0) and SIN(15:0)
is shown in Figure 3. This timing is independent of whether
the output data represents the phase accumulator data or the
SIN/COS Generator output.
When it is desired for the output of the NCO16 to be switched
back and forth between sine/cosine and the phase
accumulator, a circuit such as the one shown in Figure 4 could
be used. In this case, the sinusoidal output cannot be
interrupted, so the phase accumulator must be read out
between samples. This is possible due to the fact that the
TEST signal is simply the control line for a multiplexer on the
output of the SIN/COS Generator, but carries with it a
limitation on the maximum possible clock rate. Since TEST is
a synchronous input, the output of the NCO16 must be either
driven by the SIN/COS Generator or the phase accumulator
for an entire clock cycle. Therefore, the part must be driven at
twice the desired speed at all times so there is a clock cycle
available for TEST, when necessary. Note that the processor
must be driven from the same clock that generates the NCO
clock in order to maintain synchronous operation.
MICROPROCESSOR
HSP45106
DATA
WE
ADDRESS
GND
VCC
DECODE
START
LOGIC
VCC
GND
VCC
GND
VCC
VCC
VCC
VCC
VCC
OSCILLATOR
MOD0(2:0) (15:0)
PMSEL SIN0-15
C(15:0)
WR COS(15:0)
A(2:0)
CS
ENPOREG
ENCFREG
OES
OEC
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
WRITE
WRITE
MS INPUT LS INPUT
REGISTER REGISTER
WR
CS
A0-2
C0-15
ENCFREG,
ENOFREG
COS0-15,
SIN0-15
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
NEW
FREQUENCY
DATA
CLK
FIGURE 3. NCO16 PIPELINE DELAY
MICROPROCESSOR
HSP45106
DATA
WE
ADDRESS
GND
VCC
DECODE
VCC
GND
VCC
GND
START
LOGIC
÷2
VCC
VCC
VCC
VCC
MOD0-2
PMSEL SIN0-15
C0-15
WR
COS0-15
A0-2
CS
ENPOREG
ENCFREG
OES
OEC
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
DAC
DAC
>
REGISTER
FIGURE 2. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NCO16
OSCILLATOR
FIGURE 4. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NCO16 WHILE GENERATING SINUSOID
7
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