CY2305ZC-1 データシートの表示（PDF） - Cypress Semiconductor
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CY2305ZC-1 Datasheet PDF : 19 Pages
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CY2305, CY2309
Absolute Maximum Conditions
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC input voltage (Except REF) .......... –0.5 V to VDD + 0.5 V
DC input voltage REF ........................................–0.5 V to 7 V
Storage temperature .................................. –65°C to +150°C
Junction temperature.................................................. 150°C
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2,000 V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
Supply voltage
3.0
3.6
V
TA
Operating temperature (ambient temperature)
0
70
°C
CL
Load capacitance, below 100 MHz
–
30
pF
CL
Load capacitance, from 100 MHz to 133 MHz
–
10
pF
CIN
Input capacitance
–
7
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage (power
0.05
50
ms
ramps must be monotonic)
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature
Devices
Parameter
Description
Test Conditions
Min
VIL
Input LOW voltage[6]
–
VIH
Input HIGH voltage[6]
2.0
IIL
Input LOW current
VIN = 0 V
–
IIH
Input HIGH current
VIN = VDD
–
VOL
Output LOW voltage[7]
IOL = 8 mA (–1)
–
IOH = 12 mA (–1H)
VOH
Output HIGH voltage[7]
IOH = –8 mA (–1)
2.4
IOL = –12 mA (–1H)
IDD (PD mode) Power-down supply current
REF = 0 MHz
–
IDD
Supply current
Unloaded outputs at 66.67 MHz,
–
SEL inputs at VSS
Max
0.8
–
50.0
100.0
0.4
–
12.0
32.0
Unit
V
V
μA
μA
V
V
μA
mA
Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature
Devices
Parameter[9]
Name
Test Conditions
Min Typ. Max
Unit
t1
Output frequency
30-pF load
10-pF load
10
–
100
MHz
10
133.33
MHz
tDC
Duty cycle[7] = t2 ÷ t1
Measured at 1.4 V, Fout =
40.0 50.0 60.0
%
66.67 MHz
t3
Rise time[7]
Measured between 0.8 V and 2.0 V –
–
2.50
ns
t4
Fall time[7]
Measured between 0.8 V and 2.0 V –
–
2.50
ns
t5
Output-to-output skew[7]
All outputs equally loaded
–
85
250
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge[7]
Measured at VDD/2
–
0
±350
ps
Notes
6. REF input has a threshold voltage of VDD/2.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number : 38-07140 Rev. *M
Page 5 of 19
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