CY2305ZC-1 データシートの表示（PDF） - Cypress Semiconductor
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CY2305ZC-1 Datasheet PDF : 19 Pages
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CY2305, CY2309
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
VIL
Input LOW voltage[10]
–
VIH
Input HIGH voltage[10]
2.0
IIL
Input LOW current
VIN = 0 V
–
IIH
Input HIGH current
VIN = VDD
–
VOL
Output LOW voltage[11] IOL = 8 mA (–1)
–
IOH =12 mA (–1H)
VOH
Output HIGH voltage[11] IOH = –8 mA (–1)
2.4
IOL = –12 mA (–1H)
IDD (PD mode) Power-down supply
REF = 0 MHz
–
current
IDD
Supply current
Unloaded outputs at 66.67 MHz, SEL inputs at VSS
–
Max
0.8
–
50.0
100.0
0.4
–
25.0
35.0
Unit
V
V
μA
μA
V
V
μA
mA
Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices
Parameter[12]
Name
Test Conditions
Min Typ Max Unit
t1
Output frequency
30 pF load
10 pF load
tDC
Duty cycle[11] = t2 ÷ t1
Measured at 1.4 V, Fout = 66.67 MHz
t3
Rise time[11]
Measured between 0.8 V and 2.0 V
t4
Fall time[11]
Measured between 0.8 V and 2.0 V
t5
Output-to-output skew[11] All outputs equally loaded
t6A
Delay, REF rising edge to
CLKOUT rising edge[11]
Measured at VDD/2
10
– 100 MHz
10
133.33 MHz
40.0 50.0 60.0
%
–
– 2.50
ns
–
– 2.50
ns
–
85 250
ps
–
– ±350 ps
t6B
t7
tJ
tLOCK
Delay, REF rising edge to
CLKOUT rising edge[11]
Measured at VDD/2. Measured in PLL Bypass Mode,
CY2309 device only.
1
Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins of devices
–
Cycle-to-cycle jitter[11] Measured at 66.67 MHz, loaded outputs
–
PLL lock time[11]
Stable power supply, valid clock presented on REF
–
pin
5 8.7
ns
– 700
ps
70 200
ps
– 1.0
ms
Notes
10. REF input has a threshold voltage of VDD/2.
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
12. All parameters specified with loaded outputs
Document Number : 38-07140 Rev. *M
Page 7 of 19
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