NQ6311 データシートの表示（PDF） - Unspecified
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NQ6311 Datasheet PDF : 902 Pages
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21.1
21.2
21.3
PCI Configuration Registers (LPC I/F – D31:F0) ................................................... 665
21.1.1 VID – Vendor Identification Register (LPC I/F – D31:F0).......................... 666
21.1.2 DID – Device Identification Register (LPC I/F – D31:F0) .......................... 666
21.1.3 PCICMD – PCI COMMAND Register (LPC I/F – D31:F0) ............................ 666
21.1.4 PCISTS – PCI Status Register (LPC I/F – D31:F0) ................................... 667
21.1.5 RID – Revision Identification Register (LPC I/F – D31:F0) ........................ 667
21.1.6 PI – Programming Interface Register (LPC I/F – D31:F0) ......................... 668
21.1.7 SCC – Sub Class Code Register (LPC I/F – D31:F0)................................. 668
21.1.8 BCC – Base Class Code Register (LPC I/F – D31:F0) ............................... 668
21.1.9 PLT – Primary Latency Timer Register (LPC I/F – D31:F0) ....................... 668
21.1.10 HEADTYP – Header Type Register (LPC I/F – D31:F0) ............................. 668
21.1.11 SS – Sub System Identifiers Register (LPC I/F – D31:F0) ........................ 668
21.1.12 PMBASE – ACPI Base Address Register (LPC I/F – D31:F0) ...................... 669
21.1.13 ACPI_CNTL – ACPI Control Register (LPC I/F – D31:F0)........................... 669
21.1.14 GPIOBASE – GPIO Base Address Register (LPC I/F – D31:F0)................. 670
21.1.15 GC – GPIO Control Register (LPC I/F – D31:F0)...................................... 670
21.1.16 PIRQ[n]_ROUT – PIRQ[A,B,C,D] Routing Control Register
(LPC I/F – D31:F0)............................................................................. 670
21.1.17 SIRQ_CNTL – Serial IRQ Control Register
(LPC I/F – D31:F0)............................................................................. 671
21.1.18 PIRQ[n]_ROUT – PIRQ[E,F,G,H] Routing Control Register
(LPC I/F – D31:F0)............................................................................. 671
21.1.19 LPC_I/O_DEC – I/O Decode Ranges Register
(LPC I/F – D31:F0)............................................................................. 672
21.1.20 LPC_EN – LPC I/F Enables Register (LPC I/F – D31:F0) ........................... 672
21.1.21 GEN1_DEC – LPC I/F Generic Decode Range 1 Register
(LPC I/F – D31:F0)............................................................................. 673
21.1.22 GEN2_DEC – LPC I/F Generic Decode Range 2 Register
(LPC I/F – D31:F0)............................................................................. 674
21.1.23 FWH_SEL1 – Firmware Hub Select 1 Register
(LPC I/F – D31:F0)............................................................................. 674
21.1.24 FWH_SEL2 – Firmware Hub Select 2 Register
(LPC I/F – D31:F0)............................................................................. 675
21.1.25 FWH_DEC_EN1 – Firmware Hub Decode Enable Register
(LPC I/F – D31:F0)............................................................................. 675
21.1.26 BIOS_CNTL – BIOS Control Register
(LPC I/F – D31:F0)............................................................................. 677
21.1.27 RCBA – Root Complex Base Address Register
(LPC I/F – D31:F0)............................................................................. 677
DMA I/O Registers (LPC I/F – D31:F0) ................................................................ 677
21.2.1 DMABASE_CA – DMA Base and Current Address
Registers (LPC I/F – D31:F0) ............................................................... 679
21.2.2 DMABASE_CC – DMA Base and Current Count Registers
(LPC I/F – D31:F0)............................................................................. 679
21.2.3 DMAMEM_LP – DMA Memory Low Page Registers
(LPC I/F – D31:F0)............................................................................. 680
21.2.4 DMACMD – DMA Command Register (LPC I/F – D31:F0).......................... 680
21.2.5 DMASTA – DMA Status Register (LPC I/F – D31:F0)................................ 681
21.2.6 DMA_WRSMSK – DMA Write Single Mask Register
(LPC I/F – D31:F0)............................................................................. 681
21.2.7 DMACH_MODE – DMA Channel Mode Register
(LPC I/F – D31:F0)............................................................................. 682
21.2.8 DMA Clear Byte Pointer Register (LPC I/F – D31:F0) ............................... 682
21.2.9 DMA Master Clear Register (LPC I/F – D31:F0)....................................... 683
21.2.10 DMA_CLMSK – DMA Clear Mask Register (LPC I/F – D31:F0).................... 683
21.2.11 DMA_WRMSK – DMA Write All Mask Register
(LPC I/F – D31:F0)............................................................................. 683
Timer I/O Registers (LPC I/F – D31:F0) .............................................................. 683
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Intel® 631xESB/632xESB I/O Controller Hub Datasheet
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