PI6C673FA データシートの表示（PDF） - Pericom Semiconductor

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PI6C673FA

133 MHz Single Chip Mobile Clock Supports 440 BX™/VIAPromedia™ Chipset with Pentium II™/Pentium III™/Celeron™

Pericom Semiconductor 

PI6C673F 133 MHz Single Chip Mobile Clock

Supports 440BX™/ VIA Promedia™ Chipset

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Byte 1: CPU, 24/48 MHz Active/Inactive Register

(1 = enabled, 0 = stopped, output held LOW)

Bit

Pin # Power-Up Default

Description

Bit 7

22

1

48/24 MHzA (Enabled/Stopped)

Bit 6

23

1

48/24 MHzB (Enabled/Stopped)

Bit 5

N/A

X

(Reserved)

Bit 4

N/A

Bit 3

38

1

(Reserved)

1

SDRAM_FB (Enabled/Stopped)

Bit 2

–

1

(Reserved)

Bit 1

41

1

CPUCLK1 (Enabled/Stopped)

Bit 0

42

1

CPUCLK0 (Enabled/Stopped)

Byte 2: PCI Active/Inactive Register

(1 = enable, 0 = stopped, output held LOW)

Bit

Pin # Power-Up Default

Description

Bit 7

N/A

x

Reserved

Bit 6

8

1

PCICLK_F (Enabled/Stopped)

Bit 5

16

1

PCICLK5 (Enabled/Stopped)

Bit 4

14

1

PCICLK4 (Enabled/Stopped)

Bit 3

13

1

PCICLK3 (Enabled/Stopped)

Bit 2

12

1

PCICLK2 (Enabled/Stopped)

Bit 1

11

1

PCICLK1 (Enabled/Stopped)

Bit 0

9

1

PCICLK0 (Enabled/Stopped)

Byte 3: SDRAM Active/Inactive Register

(1= enabled, 0 = stopped, output held low)

Bit Pin # Power-Up Default

Description

Bit 7 N/A

1

(Reserved)

Bit 6 N/A

1

(Reserved)

Bit 5

29

1

SDRAM5 (Enabled/Stopped)

Bit 4

30

1

SDRAM4 (Enabled/Stopped)

Bit 3

32

1

SDRAM3 (Enabled/Stopped)

Bit 2

33

1

SDRAM2 (Enabled/Stopped)

Bit 1

35

1

SDRAM1 (Enabled/Stopped)

Bit 0

36

1

SDRAM0 (Enabled/Stopped)

5

PS8400B

05/01/00

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