PI6C673FA データシートの表示（PDF） - Pericom Semiconductor
部品番号
コンポーネント説明
一致するリスト
PI6C673FA
Pericom Semiconductor
PI6C673FA Datasheet PDF : 10 Pages
| |||
PI6C673F
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
133 MHz Single Chip Mobile Clock
Supports 440 BXTM/VIAPromediaTM Chipset
with Pentium IITM/Pentium IIITM/CeleronTM
Features
Integrated clock and buffer for Pentium II/Pentium III/
Celeron processors
I2C: 2-Wire Serial Interface. Device vendor ID is readable
Edge rate control of clock output signals for EMI suppression
Eight Spread Spectrum options for optimal EMI suppression
Individual clock output enable/disable
Two CPUCLKs, with enhanced drive
Seven PCI clocks
Seven SDRAM clocks for 3 SO DIMMs.
Three 14.31818 MHz clocks
(REF2 has an enhanced output drive)
Two 48/24 MHz clocks
Low skew and low power consumption.
Extended temperature range 0°C - 85°C
Package: 48-pin 240 mil TSSOP (A)
Description
PI6C673F is the ideal low-cost solution for the 66/100/133 MHz
SDRAM-based mobile/handheld platform. It integrates high-speed,
low-noise, low-jitter, and low-skew clock generator and SDRAM
buffers. The device supports either discrete or modular processors,
three SO DIMMs, two 48/24 MHz outputs for USB and Super I/O, and
a combination of six PCI slots and devices. Power management
controls are realized with standard control signals such as:
PWR_DWN#, CPU_STOP#, and PCI_STOP#. To further reduce
power consumption and to minimize EMI emission, each individual
output can be enabled/disabled through I2C interface.
A wide range of SSC (Spread Spectrum Clock) options allow users
to choose the best mode for minimal EMI. Generous power supply
pins ensure that the device will have low noise and high performance.
Block Diagram
XTAL_IN
XTAL_OUT
PWR_DWN#
CPU_STOP#
PCI_STOP#
S1, S0
Xtal
OSC
STOP
PLL1
STOP
Control
Logic
PLL2
/2
SDRAM_IN
SDATA
I2C
SCLK
Logic
Pin Configuration
REF[0-2]
CPUCLK[0-1]
PCICLK[0-5]
PCICLK_F
48/24MHzA/B
SDRAM_FB
SDRAM[0-5]
REF1
REF0
Vss
XTAL_IN
XTAL_OUT
S1
Vddq_3
PCICLK_F
PCICLK0
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq_3
PCICLK5
Vss
S0
SDATA
SCLK
Vddq_3
48/24MHzA
48/24MHzB
Vss
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
11
48-Pin
A
39
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
Vddq_3
N/C
Vddq_3
REF2
PWR_DWN#
Vss
CPUCLK0
CPUCLK1
Vddq_2
SDRAM_IN
SDRAM_FB
Vss
SDRAM0
SDRAM1
Vddq_3
SDRAM2
SDRAM3
Vss
SDRAM4
SDRAM5
Vddq_3
CPU_STOP#
PCI_STOP#
Vddq_3
1
PS8400B
05/01/00
Share Link: