STPCE1 データシートの表示（PDF） - STMicroelectronics

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STPCE1

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

s X86 Processor core

s Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

s Can access up to 4GB of external memory.

s 8KByte unified instruction and data cache

with write back and write through capability.

s Parallel processing integral floating point unit,

with automatic power down.

s Clock core speeds up to of 100 MHz in x1

clock mode and 133MHz in x2 mode.

s Fully static design for dynamic clock control.

s Low power and system management modes.

s SDRAM Controller

s 64-bit data bus.

s Up to 100MHz SDRAM clock speed.

s Supports up to 128 MB system memory.

s Supports 16-, 64- and 128-Mbit memories.

s Supports up to 4 memory banks.

s Supports buffered, non buffered, registered

DIMMs

s 4-line write buffers for CPU to DRAM and PCI

to DRAM cycles.

s 4-line read prefetch buffers for PCI masters.

s Programmable latency

s Programmable timing for DRAM parameters.

s Supports -8, -10, -12, -13, -15 memory parts

s Supports memory hole between 1MB and

8MB for PCI/ISA busses.

s PCI Controller

s Compliant with PCI 2.1 specification.

s Integrated PCI arbitration interface. Up to 3

masters can connect directly. External logic

allows for greater than 3 masters.

s Translation of PCI cycles to ISA bus.

s Translation of ISA master initiated cycle to

PCI.

s Support for burst read/write from PCI master.

s 0.25X, 0.33X and 0.5X Host clock PCI clock.

s ISA master/slave

s Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

s Supports programmable extra wait state for

ISA cycles

s Supports I/O recovery time for back to back

I/O cycles.

s Fast Gate A20 and Fast reset.

s Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

s Supports flash ROM.

s Supports ISA hidden refresh.

s Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host

bus. NSP compliant.

s 16-bit I/O decoding.

s Local Bus interface

s Multiplexed with ISA/DMA/Timer functions.

s High speed, low latency bus.

s Supports 32-bit Flash burst.

s 16-bit data bus with word steering capability.

s Separate memory and I/O address spaces.

s Programmable timing (Host clock granularity)

s Supports 2 cachable banks of 16MB flash

devices with boot block shadowed to

0x000F0000.

s 2 Programmable Flash/EPROM Chip Select.

s 4 Programmable I/O Chip Select.

s 2-level hardware key protection for Flash boot

block protection.

s 24 bit address bus.

s EIDE Controller

s Compatible with EIDE (ATA-2).

s Backward compatibility with IDE (ATA-1).

s Supports up to 4 IDE devices

s Supports PIO and Bus Master IDE

s Concurrent channel operation (PIO & DMA

modes) - 4 x 32-Bit Buffer FIFO per channel

s Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

s Bus Master with scatter/gather capability.

s Multi-word DMA support for fast IDE drives.

s Individual drive timing for all four IDE devices.

s Supports both legacy & native IDE modes.

s Supports hard drives larger than 528MB.

s Support for CD-ROM and tape peripherals.

s Integrated Peripheral Controller

s 2X8237/AT compatible 7-channel DMA

controller.

s 2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

s Three 8254 compatible Timer/Counters.

s Co-processor error support logic.

s Supports external RTC.

s Power Management

s Four power saving modes: On, Doze,

Standby, Suspend.

2/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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