STPCE1 データシートの表示（PDF） - STMicroelectronics

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STPCE1

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

PIN DESCRIPTION

2. PIN DESCRIPTION

2.1. INTRODUCTION

The STPC Elite integrates most of the

functionalities of the PC architecture. As a result,

many of the traditional interconnections between

the host PC microprocessor and the peripheral

devices are totally internal to the STPC Elite. This

offers improved performance due to the tight

coupling of the processor core and these

peripherals. As a result many of the external pin

connections are made directly to the on-chip

peripheral functions.

Figure 2-1 shows the STPC Elite external

interfaces. It defines the main buses and their

function. Table 2-1 describes the physical

implementation listing signals type and their

functionality. Table 2-2 provides a full pin listing

and description of pins. Table 2-7 provides a full

listing of pin locations of the STPC Elite package

by physical connection.

Table 2-1. Signal Description

Group name

Basic Clocks reset & Xtal

Memory Interface

PCI interface

ISA

IDE

Local Bus

Grounds

VDD

Miscellaneous

GPIO

Unconnected

Total Pin Count

Qty

6

96

56

79

34

90

50

69

22

8

16

25

388

Note: Several interface pins are multiplexed with

other functions, refer to Table 2-4 and Table 2-5

for further details

Figure 2-1. STPC Elite External Interfaces

x86

STPC Elite

NORTH

SDRAM I/F

96

PCI

SOUTH

SYS

ISA/IDE/LB

56

6

90

Release 1.3 - January 29, 2002

11/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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