V54C3128404V データシートの表示（PDF） - Mosel Vitelic Corporation

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V54C3128404V

128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 8M X 16 16M X 8 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

3. Read Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND READ A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

DOUT A0

DOUT B0

DOUT B1

DOUT B2

DOUT B3

DOUT A0

DOUT B0

DOUT B1

DOUT B2

DOUT B3

4.1 Read to Write Interval

(Burst Length = 4, CAS latency = 3)

T0

T1

T2

T3

T4

T5

T6

T7

CLK

DQM

COMMAND NOP

Minimum delay between the Read and Write Commands = 4+1 = 5 cycles

tDQZ

tDQW

READ A

NOP

NOP

NOP

NOP

WRITE B

NOP

T8

NOP

I/O’s

: “H” or “L”

DOUT A0

Must be Hi-Z before

the Write Command

DIN B0

DIN B1

DIN B2

V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001

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