General Description
The VSC8174 combines a clock recovery unit and data retiming with a 1:16 demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 9.953/10.66 Gb/s data stream. An on-chip Phase Locked Loop (PLL) with voltage controlled oscillator generates a 9.953/10.66 GHz clock, which remains phase locked to the incoming data. The clock generator requires a 19.44/20.83 MHz PECL reference clock input (REFCK+). The incoming data is retimed and demultiplexed into 16 parallel outputs. In addition, the input sampling point can be adjusted in voltage for optimal data recovery. The device has two output alarm conditions: Loss of Lock (LOL) reflects the lock condition of the PLL, no reference (NOREF) indicates the loss of reference clock input. A parity bit is clocked out with the 16 parallel data. The device is packaged in a 100 pin thermally enhanced Quad Flat Pack (QFP) and a 96 ball, Ball Grid Array (BGA).

FEATUREs
• 10 Gbit/sec SONET/SDH 1:16 Demux
• Integrated Clock and Data Recovery
• Input Data Sensitivity of 50mV
• Input Threshold Voltage Adjustment
• Operation at 9.953 to 10.66 Gb/s rates
• Low Speed LVDS Outputs
• 19.44/20.83 Ref Clock Input
• Lock Error Detect, Lock to REFCLK
• Data Polarity Invert
• Bit Order Swap
• High Speed 9.9 to 10.7 Ghz Clock Output
• Parity Bit Calculation
• Low Power Dissipation
• Single +3.3V Supply
• Meets SONET OC-192 and SDH STM-64 Jitter Tolerance Requirements