DESCRIPTION
The UT54ACS74 and the UT54ACTS74 contain two independent D-type positive triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirement is transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The devices are characterized over full military temperature range of -55°C to +125°C.

FEATURES
❐ 1.2μ CMOS
   - Latchup immune
❐ High speed
❐ Low power consumption
❐ Single 5 volt supply
❐ Available QML Q or V processes
❐ Flexible package
   - 14-pin DIP
   - 14-lead flatpack
❐ UT54ACS74 - SMD 5962-96534
❐ UT54ACTS74 - SMD 5962-96535