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SL74HC175D データシート - System Logic Semiconductor

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SL74HC175D

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System Logic Semiconductor System-Logic

The SL74HC175 is identical in pinout to the LS/ALS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive-going edge of the Clock input.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices

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Quad D Flip−Flop with Common Clock and Reset
ON Semiconductor
Quad D Flip-Flop with Common Clock and Reset
Kodenshi Auk Co., LTD
Quad D Flip-Flop with Common Clock and Reset ( Rev : 2014 )
ON Semiconductor
Quad D Flip-Flop with Common Clock and Reset
Kodenshi Auk Co., LTD
Quad D Flip−Flop with Common Clock and Reset
ON Semiconductor
Quad D Flip-Flop with Common Clock and Reset
ON Semiconductor
Quad D Flip−Flop with Common Clock and Reset
ON Semiconductor
Quad D Flip-Flop with Common Clock and Reset
Kodenshi Auk Co., LTD
Quad D Flip-Flop with Common Clock and Reset ( Rev : 2012 )
ON Semiconductor
Quad D Flip-Flop With Common Clock & Reset
ON Semiconductor

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