Description
The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface.

FEATUREs
Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
„Meets OC-192 GR-253-CORE jitter specifications
Clock or crystal input with manual clock selection
Clock output selectable signal format (LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
Supports various frequency translations for Synchronous Ethernet
LOL, LOS alarm outputs
I2C or SPI programmable
On-chip voltage regulator for 1.8 V ±5%, 2.5 or 3.3 V ±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant

APPLICATIONs
SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
Synchronous Ethernet
Test and measurement
Discrete PLL replacement
Broadcast video