Features
RISC architecture
Static Design & Synthesizable design
Bus interface
   - Multiplexed address and Data bus which compatible with 80C188 microprocessor
   - Supports nonmultiplexed address bus [A19 : A0]
   - 1M byte memory address space
   - 64K byte I/O space
Software compatible with the 80C186
Support two Asynchronous serial channel with hardware handshaking signals.
Support serial port with DMA transfers
Supports 32 PIO pins
PSRAM (Pseudo static RAM) interface with auto-refresh control
Three independent 16-bit timers and one independent watchdog timer
The Interrupt controller with seven maskable external interrupts and one nonmaskable external interrupt
Two independent DMA channels
Programmable chip-select logic for Memory or I/O bus cycle decoder
Programmable wait-state generator