[QuickLogic]
PRODUCT SUMMARY
The QL16x24B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 384 logic cell field-programmable gate array (FPGA) offers 4,000 usable ASIC gates (equivalent to 7,000 PLD gates) of high-performance general-purpose logic in 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA, and 160-pin CQFP.
FEATURES
■ Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
■ High Usable Density – A 16-by-24 array of 384 logic cells provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin CQFP packages.
■ Low-Power, High-Output Drive – Standby current typically 2 mA. A 16-bit counter operating at 100 MHz consumes less than 50 mA. Minimum IOL of 12 mA and IOH of 8 mA
■ Low-Cost, Easy-to-Use Design Tools – Designs entered and simulated using QuickLogics new QuickWorks® development environment, or with third-party CAE tools including Viewlogic, Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place and route on PC and workstation platforms using QuickLogic software.
■ Total of 122 I/O pins
– 114 Bidirectional Input/Output pins
– 6 Dedicated Input/High-Drive pins
– 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks
■ Input + logic cell + output delays under 6 ns
■ Chip-to-chip operating frequencies up to 110 MHz
■ Internal state machine frequencies up to 150 MHz
■ Clock skew < 0.5 ns
■ Input hysteresis provides high noise immunity
■ Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming
■ Packages are 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA, and 160-pin CQFP
■ 84-pin PLCC compatible with QL12x16B
■ 100-pin TQFP compatible with QL8x12B and QL12x16B
■ 144-pin TQFP compatible with QL24x32B
■ 0.65µ CMOS process with ViaLink programming technology