FEATURES
The PM8172 system controller is ideal for various designs of advanced set-top boxes, DVD players, game stations, and Internet terminal appliances. The PM8172 interfaces to PMC-Sierra’s RM5231A, RM7035C and RM7935 MIPS RISC processors.

CPU INTERFACE
• Connects to PMC-Sierra’s RM5231A, RM7035C, and RM7935 64-bit MIPS RISC microprocessors.
• Supports CPU bus frequencies up to 100 MHz.

SDRAM CONTROLLER
• 32-bit data bus interface.
• Supports two banks of SDRAM, up to 128 Mbytes in size.
• Provides a deep buffer for CPU to SDRAM burst transfers and for PCI to SDRAM burst transfers.
• Supports bus frequencies up to 100 MHz.

FLASH/ROM INTERFACE
• Supports Flash memory area up to 64 Mbytes, with 8-bit, 16-bit, and 32-bit data access capability.
• Supports a ROM area size up to 4 Mbytes, with 8-bit, 16-bit, and 32-bit data access capability.
• Supports a maximum of 12 chip-select signals.
• Shared with a 68K-like peripheral bus.

PERIPHERAL BUS CONTROLLER
• Provides a 68K-like bus interface.
• Does not require an external latch for addressing.
• Provides an 8-bit and 16-bit data bus interface.
• Shared with the Flash/ROM interface.
• Supports up to four DMA channels.
• Provides cycle posting to avoid performance hits from slower devices.

PCI BUS CONTROLLER
• Provides CPU to PCI buffers for burst
transfers.

• Provides a PCI arbiter that supports up
to five individual bus master devices.
• Supports 33 MHz bus frequency.
• Provides a 32-bit data bus interface.

INTERRUPT CONTROLLER
• Supports a maskable interrupt to the CPU and a non-maskable interrupt to the CPU for severe events.
• The priority order of interrupt request lines can be assigned by software.
• Module interrupts can be masked on/off independently by setting the corresponding mask registers.

DMA CONTROLLER
• Supports four channel requests for LPC or ECP DMA mode data transfers.
• Supports PCI bus master accessing to the SDRAM.

CHAINING DMA CONTROLLER
• Supports four independent software DMA channels for transferring data between SDRAM and PCI devices.
• Supports chaining and non-chaining modes.
• Supports rotating and fixed priority types. (Continue..)