FEATURES
GENERAL
• ATM and Packet over SONET/SDH (POS) OC-12c (622 Mbit/s) PHY
• Provides on-chip clock and data recovery and clock synthesis
• Exceeds Bellcore-GR-253 jitter requirements
• Inserts and extracts ATM cells or POS packets into/from SONET SPE
• Filters and captures Automatic Protection Switch bytes (K1,K2) and detects APS byte failure
• Detects signal degrade and signal failure thresholds crossing alarms
• Captures and debounces synchronization status byte (S1)
• Extracts and Inserts the 16 or 64-byte section trace (J0) and path trace (J1) messages
• Extracts and inserts section/line data communication channels (DCC)
• Provides circuitry to meet holdover, wander and long term stability
• Provides a generic 8-bit microprocessor interface for device control and register access
• Provides standard IEEE 1149.1 JTAG test port for boundary scan

APPLICATIONS
• WAN and Edge ATM switches
• Multiprotocol switches
• Layer 3 switches
• Routers, Packet switches and Hubs