[International-Cmos]

General Description
The PEEL18CV8 is a Programmable Electrically Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs. The PEEL18CV8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today.

FEATUREs
■ Multiple Speed Power, Temperature Options
    - VCC = 5 Volts ±10%
    - Speeds ranging from 5ns to 25 ns
    - Power as low as 37mA at 25MHz
    - Commercial and industrial versions available
■ CMOS Electrically Erasable Technology
    - Superior factory testing
    - Reprogrammable in plastic package
    - Reduces retrofit and development costs
■ Development / Programmer Support
    - Third party software and programmers
    - ICT PLACE Development Software and PDS-3 programmer
    - PLD-to-PEEL JEDEC file translator Architectural Flexibility
    - Enhanced architecture fits in more logic
    - 74 product terms x 36 input AND array
    - 10 inputs and 8 I/O pins
    - 12 possible macrocell configurations
    - Asynchronous clear
    - Independent output enables
    -- 20 Pin DIP/SOIC/TSSOP and PLCC
■ Application Versatility
    - Replaces random logic
    - Super sets PLDs (PAL, GAL, EPLD)
    - Enhanced Architecture fits more logic than ordinary PLDs