General Description
The MT28F1284W18 is a high-performance, high-density, nonvolatile memory solution that can significantly improve system performance. This architecture features a multipartition configuration that supports READ-While-PROGRAM/ERASE operations with no latency. An 8Mb partition size enables optimal design flexibility.
FEATUREs
Dedicated commands to decrease programming times for both in-factory and in-system operations
Fast programming algorithm (FPA) for fast PROGRAM operation
16-word page
Flexible 8Mb multipartition architecture
Single word (16-bit) data bus
Support for true concurrent operation with zero latency
Basic configuration:
• 135 individually programmable/erasable blocks
• 16 partitions (8Mb each for code and data storage)
Operating Voltage
• VCC = 1.70V (MIN)–1.95V (MAX)
• VCCQ = 1.70V (MIN)–2.24V (MAX)
VPP = 1.8V (TYP) for in-system PROGRAM/ERASE
• 12V ±5% (HV) VPP tolerant (factory programming compatibility)
Random access time: 60ns @ 1.70V VCC
Burst mode read access
• MAX clock rate: 66 MHz (tCLK = 15ns)
• MAX clock rate: 54 MHz (tCLK = 18.5ns)
• Burst latency 60ns @1.70V VCC and 66 MHz
• 4 word, 8 word, 16 word, and continuous burst modes
• tACLK: 14ns @ 1.70V VCC and 54 MHz
• tACLK: 11ns @ 1.70V VCC and 66 MHz
Page mode read access
• Interpage read access: 60ns @ 1.70V VCC
• Intrapage read access: 15ns @ 1.70V VCC
Low power consumption (VCC = 1.95V)
• Burst read @ 66 MHz <10mA (TYP)
• Standby < 50µA(TYP)
• Automatic power save (APS)
Enhanced program and erase suspend options
• ERASE-SUSPEND-to-READ within same partition
• PROGRAM-SUSPEND-to-READ within same partition
• ERASE-SUSPEND-to-PROGRAM within same partition
Dual 64-bit chip protection registers for security purposes
Cross-compatible command support
• Extended command set
• Common flash interface
Programmable WAIT# configuration
Clock suspend
100,000 ERASE cycles per block