DESCRIPTION
The M54HC573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology.
This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q outputs will follow the data input precisely. When LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.
While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while is at high level the outputs will be in a high impedance state.
The 3-State output configuration and the wide choice of outline make bus organized system simple.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 573
■ SPACE GRADE-1: ESA SCC QUALIFIED
■ 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST
■ NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION
■ DEVICE FULLY COMPLIANT WITH SCC-9202-072