DESCRIPTION
The M54/74HC109 is a high speed CMOS DUAL J K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology.
It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
In accordance with the logic level on the J and K input is device changes state on positive going transitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished bya low logic level on the corresponding input.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED
   fMAX = 63 MHz (TYP.) AT VCC = 5 V
■ LOW POWER DISSIPATION
   ICC = 2 µA (MAX.) AT TA = 25 °C
■ HIGH NOISE IMMUNITY
   VNIH = VNIL = 28 % VCC (MIN.)
■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
■ SYMMETRICAL OUTPUT IMPEDANCE
  |IOH| = IOL = 4 mA (MIN.)
■ BALANCED PROPAGATION DELAYS
   tPLH = tPHL
■ WIDE OPERATING VOLTAGE RANGE
   VCC (OPR) = 2 V TO 6 V
■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS109