OVERVIEW
ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows.

FEATURES
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
                     Vdd     Vddq
    IS42/45S16320B  3.3V  3.3V
    IS42S86400B      3.3V  3.3V
• LVTTL interface
• Programmable burst length
  – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Available in 54-pin TSOP-II and 54-ball W-BGA (x16 only)
• Operating Temperature Range:
   Commercial: 0°C to +70°C
   Industrial: -40°C to +85°C
   Automotive, A1: -40°C to +85°C