The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating filters.

FEATUREs
• This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR
• 10-Bit Data and Coefficients
• On-Board Storage for 32 Programmable Coefficient Sets
• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 20-Bit Data and Coefficients
• Programmable Decimation to 16
• Programmable Rounding on Output
• Standard Microprocessor Interface
• 33MHz, 25.6MHz Versions

APPLICATIONs
• Quadrature, Complex Filtering
• Correlation
• Image Processing
• PolyPhase Filtering
• Adaptive Filtering