Features
• Generates all clocks required for single and two-way multi-processor (MP) platforms, including:
   ◆ Four differential current-mode Host clock pairs
   ◆ Four 66.67MHz 3.3V CK66 clock outputs
   ◆ Ten 33.3MHz 3.3V PCI clock outputs
   ◆ Two 3.3V Memory Reference clock outputs
   ◆ Two 48MHz 3.3V CK48 clock outputs
   ◆ Two buffered copies of the crystal reference
• Control of current-mode Host clocks via IREF current programming pin and ISEL_0:1 current multiplier pins
• Host clock frequency selection via the SEL_A, SEL_B, and SEL133/100# pins
• Active-low PWR_DWN# signal allows one complete clock cycle on each clock outputs and then shuts down the crystal oscillator, PLLs, and outputs
• Spread-spectrum modulation (-0.5% at 31.5kHz) of SSCG PLL clocks, enabled via SS_EN# input
• Supports test mode and tristate output control to facilitate board testing
• Available in a 56-pin SSOP and TSSOP